# Building My Own CPU - Part 2: Simulation # 制造我自己的 CPU - 第二部分：仿真 --- ## Table of Contents / 目录 *[Simulation v.s. IRL / 仿真与现实](#simulation-vs-irl) * [Clock / 时钟](#clock) *[Registers / 寄存器](#registers) * [ALU / 算术逻辑单元 (ALU)](#alu) * [RAM / 随机存取存储器 (RAM)](#ram) *[Counters / 计数器](#counters) * [ROM / 只读存储器 (ROM)](#rom) *[Connecting all together / 将一切连接起来](#connecting-all-together) --- This is part 2 of a series about designing and building my own 8-bit CPU! Part 1 can be found here:[Building My Own CPU - Part 1](/2025/04/29/building-my-own-cpu-wcpu-part-1) 这是关于设计和制造我自己的 8 位 CPU 系列的第二部分！第一部分可以在这里找到：[制造我自己的 CPU - 第一部分](/2025/04/29/building-my-own-cpu-wcpu-part-1) Before getting into schematics and PCB design and things like that, I need to make quite a lot of decisions. If I could just think really hard and a perfectly formed PCB would pop out, that would be great. But that’s just not how my brain works. I need to see it to build it. 在深入研究原理图、PCB 设计以及诸如此类的事情之前，我需要做出许多决定。如果我只需绞尽脑汁地想，就能变出一块完美成型的 PCB，那当然很好。但这根本不是我的大脑运作方式。我需要先看到它，才能把它造出来。 I’m addition to *that*, I’m trying to avoid too much breadboarding which leaves but one option: simulation. 除此之外，我还想尽量避免过多地使用面包板（breadboarding），这就只剩下一个选择了：仿真。 I fired up good old [Logisim-Evolution](https://github.com/logisim-evolution/logisim-evolution) and got to work. 我启动了老伙计[Logisim-Evolution](https://github.com/logisim-evolution/logisim-evolution) 开始工作。

Simulation v.s. IRL / 仿真与现实

There are some gotchas with simulating a CPU, mostly around how virtual circuits behave vs their real life counterparts. For example, on a rising clock edge you may be able to output from RAM and latch the value into a register at the same time. In real life the RAM will take more time to settle after the address lines are asserted (e.g. 100-200ns) than the register does to latch (e.g. 10-20ns). 在对 CPU 进行仿真时会有一些隐患，主要集中在虚拟电路与现实世界中对应电路的行为差异上。例如，在时钟的上升沿，你（在仿真中）也许能够同时从 RAM 输出数据并将其锁存（latch）到寄存器中。但在现实生活中，地址线置位后，RAM 需要更长的时间才能稳定输出（例如 100-200 纳秒），而寄存器锁存数据所需的时间要短得多（例如 10-20 纳秒）。 This basically means that our clock will need to be “biphasic”. That is, slow stuff should happen on the rising edge, take its time to settle, then fast things should happen on the falling edge. 这基本上意味着我们的时钟需要是“双相（biphasic）”的。也就是说，较慢的操作应该在上升沿触发并花时间稳定，然后较快的操作应该在下降沿触发。 This limits the “width” of our clock pulse to the slowest component in the circuit. If we go any faster we will see weirdness. If we said that 200ns is the slowest component then technically that means we can run our clock at maximum of 5MHz. However that doesn’t take into account additive propagation delays (e.g. 2 registers added together will have twice the overall propagation delay). 这将我们时钟脉冲的“宽度”限制在了电路中最慢元件的速度上。如果我们运行得再快一点，就会出现异常。如果我们假设 200 纳秒是最慢元件的延迟，那么理论上意味着我们的时钟最高只能运行在 5MHz。但这还没有考虑到累加的传播延迟（propagation delays）（例如，2 个寄存器串联在一起会产生两倍的总传播延迟）。 This lets us set a nice goal of a max clock speed of about 4MHz which is plenty fast. 这让我们设定了一个不错的目标：最大时钟速度约为 4MHz，这已经足够快了。 These delays aren’t as much of a factor in the simulator, it’s just something we need to be aware of when starting out. 这些延迟在模拟器中并不是什么大问题，但这只是我们在开始时需要意识到的事情。

Clock / 时钟

This is quite easy in Logisim since it has a Clock element you can use, enable and disable with `⌘K`, as well as single step using `⌘T`. The only 2 things I added here are an inverted version of the clock signal (`CLKn`) and `AND`ing it with a signal called `HLT` which will allow the computer to stop itself by setting `HLT` high. 这在 Logisim 中非常简单，因为它有一个时钟（Clock）元件供你使用，可以通过 `⌘K` 启用和禁用，还可以使用 `⌘T` 进行单步执行。我在这里只添加了两样东西：一个是反相的时钟信号（`CLKn`），另一个是将它与名为 `HLT` 的信号进行逻辑与（`AND`）操作。通过将 `HLT` 置为高电平，计算机就可以停止自身的运行。

Registers / 寄存器

To speed up the process, I made a reusable register block and will use it for all of the registers in the build such as `A`, `B`, instruction register, etc. 为了加快进度，我制作了一个可复用的寄存器模块，并将其用于本次构建中的所有寄存器，比如 `A` 寄存器、`B` 寄存器、指令寄存器等。 Generic register

The block can take in 8 bits, and has an immediate output, as well as an output controlled by the `EN` signal (using a “controlled buffer”). The `EN` signal will be used mostly when we want to output that register onto the bus. The control logic will be handling turning that on and off. We can write to the register by setting `LOAD` high, and reset it to 0 by setting `CLR` high. 这个模块可以接收 8 位数据，并具有一个即时输出，以及一个由 `EN`（使能）信号控制的输出（使用“受控缓冲器”实现）。`EN` 信号主要用于当我们想将该寄存器的数据输出到总线时。控制逻辑将负责处理它的开启和关闭。我们可以通过将 `LOAD`（加载）置为高电平来向寄存器写入数据，并通过将 `CLR`（清零）置为高电平将其重置为 0。 Generic register loaded

The registers will be triggered by the falling edge of the clock pulse. You can set registers in Logisim to be “falling edge” triggered but I’m going to just have an inverted clock signal blocks can use instead of doing that. 寄存器将由时钟脉冲的下降沿触发。你可以在 Logisim 中将寄存器设置为“下降沿触发（falling edge triggered）”，但我打算直接提供一个反相的时钟信号供模块使用，以此来替代那种设置。 Now we have a reusable block, I can just slap them down wherever. 现在我们有了可复用的模块，我就可以把它们随便放置在任何需要的地方了。 Registers in logisim

ALU / 算术逻辑单元 (ALU)

We can again take a number of shortcuts to build the adder block. Logisim has an adder component, as well as a comparator (so we can check for zero). 在构建加法器模块时，我们同样可以走一些捷径。Logisim 拥有一个加法器组件，以及一个比较器组件（这样我们就可以用来进行零检测）。 The most basic layout could look like this: 最基本的布局可能看起来像这样： ALU in logisim

This has the ability to control its output the same way as the registers do, as well as outputting the carry and zero flags that we can use later. 它的输出控制方式与寄存器相同，并且可以输出进位标志（carry flag）和零标志（zero flag），供我们稍后使用。

Adding Subtraction (pun intended) / 加上减法（双关语）

`XOR`ing the right-hand operand with the `SUB` flag and adding 1 by also passing the `SUB` flag in as the carry bit allows us to subtract numbers. 将右操作数与 `SUB`（减法）标志进行异或（`XOR`）操作，并通过将 `SUB` 标志作为进位位传入以实现加 1，这样我们就可以进行数字的减法运算了。 In this screenshot you can see the new layout, as well as a basic subtraction (3 - 1) and its result (2) on the `SUM_IMM` pin. 在这张截图中，你可以看到新的布局，以及一个基本的减法操作 (3 - 1) 及其在 `SUM_IMM` 引脚上输出的结果 (2)。 ALU working

If the result is a negative number, it is output in [two’s complement](https://en.wikipedia.org/wiki/Two%27s_complement) format like this (-2): 如果结果是一个负数，它会以[补码（two’s complement）](https://en.wikipedia.org/wiki/Two%27s_complement)格式输出，就像这样 (-2)： ALU outputting -2

It would be cool to be able to tell if we should interpret the answer as a negative or positive number. If we looked a `11111110` as a regular unsigned integer, it would be `254` in decimal. But in two’s complement it should be read as `-2`. 如果能够判断我们是否应该将答案解析为负数或正数，那就太棒了。如果我们将 `11111110` 视为常规的无符号整数，它的十进制将是 `254`。但在补码中，它应该被读作 `-2`。 If we wanted to add a new “sign flag” we can cheat in Logisim using the “>” output of our zero detector (meaning that 0 is greater than the input): 如果我们想添加一个新的“符号标志（sign flag）”，我们可以在 Logisim 中偷个懒：利用我们的零检测器的“>”输出引脚（这意味着 0 大于输入值，即负数）： ALU showing sign flag from comparitor

We will need to put some thought into how to build the zero detector and sign flag in real hardware later. This is the danger of logisim. It allows you to validate the basic ideas, bit widths, instruction formats etc. But when it’s time to build the real hardware it can be a bit of a challenge to match the behaviour. 稍后，我们需要花点心思思考如何在真实硬件中构建零检测器和符号标志。这就是 Logisim 的危险所在：它允许你验证基本概念、位宽、指令格式等，但当要在真实硬件中实现时，让硬件行为与仿真完全匹配可能会是一个不小的挑战。

RAM / 随机存取存储器 (RAM)

We can just use Logisim’s RAM module here, no need for a separate block. I set “Data bus implementation” to “One bidirectional data bus” and “Enables” to “Use line enables” (and show label). 在这里，我们可以直接使用 Logisim 的 RAM 模块，不需要单独构建。我将“数据总线实现（Data bus implementation）”设置为“一条双向数据总线（One bidirectional data bus）”，并将“使能（Enables）”设置为“使用线路使能（Use line enables）”（并显示标签）。 RAM Module

Counters / 计数器

We need a counter for the Program Counter and also the Microcode Step Counter. I’ll just use the Counter modules that come with Logisim. In real life I’ll probably use something like `74HC590` or something similar. I set the Step Counter to 4 bits since I only want a max of 16 microcode steps per instruction. The Program Counter is just default (8 bits). 我们需要为程序计数器（Program Counter）和微代码步进计数器（Microcode Step Counter）配备计数器。我直接使用 Logisim 自带的计数器模块。在现实生活中，我可能会使用像 `74HC590` 或类似的芯片。我将步进计数器设置为 4 位，因为我希望每条指令最多只有 16 个微代码步骤。程序计数器则使用默认设置（8 位）。 Step Counter and Program Counter

These are Rising Edge triggered again, but I will hook their clocks up to the aforementioned `CLKn` signal to separate their latching from the RAM/ROM outputs. 它们同样是上升沿触发的，但我将把它们的时钟连接到前面提到的反相时钟信号 `CLKn`，以便将它们的锁存时间与 RAM/ROM 的输出时间错开。

ROM / 只读存储器 (ROM)

In place of EEPROMs in Logisim we can just use the ROM module. I set them to 12 bit addresses, and in my case I need 3. 在 Logisim 中，我们可以直接使用 ROM 模块来替代现实中的 EEPROM。我将它们设置为 12 位地址，在我的设计中，我需要 3 个这样的模块。 ROM modules

The reason for 12-bit addresses is that the microcode address will be laid out like this: 采用 12 位地址的原因是，微代码的地址将按照以下格式排列： ```text | FLAGS |INSTRUCTION| STEP | | - - - | - - - - - | - - - - | | 3 bit | 5 bit | 4 bit | ``` * 3 bits for flags: `CF`, `ZF`, `SF` **3 位用于标志（Flags）：`CF`（进位）、`ZF`（零）、`SF`（符号）** * 5 bits for instruction opcodes (max 32 different instructions) **5 位用于指令操作码（最多支持 32 种不同的指令）** * 4 bits for the T-Step (16 possible microcode steps) **4 位用于 T-Step（即时钟节拍，支持 16 个可能的微代码步骤）** And then I have the ability for up to 24 different Control Lines to be asserted as a result. 这样一来，我就有能力根据这些输入，最多同时置位 24 根不同的控制线。

Connecting all together / 将一切连接起来

Not sure of the best way to convey this via a blog post, so I will just upload a really big screenshot 我不确定在一篇博客文章中展示这些的最佳方式是什么，所以我直接上传一张超大的截图吧：

There’s quite a few things in here that I haven’t gotten into, such has the microcode, instruction set, and my custom “assembler” and “development environment” which I will save for the next part. I also created an emulator! 这里面还有很多我尚未深入探讨的内容，比如微代码、指令集，以及我自定义的“汇编器”和“开发环境”，这些我将留到下一部分再讲。我还创建了一个模拟器！